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1 ltc1417 low power 14-bit, 400ksps sampling adc converter with serial i/o a 400khz, 14-bit sampling a/d converter in a narrow 16-lead ssop package effective bits and signal-to-(noise + distortion) vs input frequency the ltc ? 1417 is a low power, 400ksps, 14-bit a/d con- verter. this versatile device can operate from a single 5v or 5v supplies. an onboard high performance sample-and- hold, a precision reference and internal trimming minimize external circuitry requirements. the low 20mw power dissipation is made even more attractive with two user- selectable power shutdown modes. the ltc1417 converts 0v to 4.096v unipolar inputs when using a 5v supply and 2.048v bipolar inputs when using 5v supplies. dc specs include 1.25lsb inl, 1lsb dnl and no missing codes over temperature. outstanding ac performance includes 81db s/(n + d) and 95db thd at a nyquist input frequency of 200khz. the internal clock is trimmed for 2 m s maximum conver- sion time. a separate convert start input and a data ready signal (busy) ease connections to fifos, dsps and microprocessors. n 16-pin narrow ssop package (so-8 footprint) n sample rate: 400ksps n 1.25lsb inl and 1lsb dnl max n power dissipation: 20mw (typ) n single supply 5v or 5v operation n serial data output n no missing codes over temperature n power shutdown: nap and sleep n external or internal reference n differential high impedance analog input n input range: 0v to 4.096v or 2.048v n 81db s/(n + d) and C 95db thd at nyquist n high speed data acquisition n digital signal processing n isolated data acquisition systems n audio and telecom processing n spectrum instrumentation , ltc and lt are registered trademarks of linear technology corporation. features descriptio u applicatio s u s/h 14 buffer 8k 10 f 10 f refcomp a in a in + v ref 4.096v 5v ltc1417 14-bit adc serial port dgnd 10 15 5 3 4 2 1 1417 ta01 v ss (0v or 5v) agnd extclkin sclk clkout d out v dd 16 timing and logic 2.5v reference busy rd convst shdn 1 f 6 7 8 9 14 12 13 11 input frequency (hz) 4 effective bits s/(n + d) (db) 6 8 10 12 10k 100k 1m 1417 ta02 2 1k 14 86 80 74 68 62 equivale t block diagra w u
2 ltc1417 (notes 1, 2) positive supply voltage (v dd ) .................................. 6v negative supply voltage (v ss ) bipolar operation only .......................... C 6v to gnd total supply voltage (v dd to v ss ) bipolar operation only ....................................... 12v analog input voltage (note 3) unipolar operation .................. C 0.3v to (v dd + 0.3v) bipolar operation............ (v ss C 0.3) to (v dd + 0.3v) digital input voltage (note 4) unipolar operation ............................... C 0.3v to 10v bipolar operation.........................(v ss C 0.3v) to 10v digital output voltage unipolar operation ................... C 0.3 to (v dd + 0.3v) bipolar operation........... (v ss C 0.3v) to (v dd + 0.3v) power dissipation ............................................. 500mw operating temperature range ltc1417c .............................................. 0 c to 70 c ltc1417i ............................................ C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio order part number t jmax = 110 c, q ja = 95 c/w ltc1417 ltc1417a parameter conditions min typ max min typ max units resolution l 14 14 bits no missing codes l 13 14 bits integral linearity error (note 7) l 0.8 2 0.5 1.25 lsb differential linearity error l 0.7 1.5 0.35 1 lsb transition noise (note 12) 0.33 0.33 lsb rms offset error external reference (note 8) l 5 20 2 10 lsb full-scale error internal reference 15 60 15 60 lsb external reference = 2.5v 5 30 5 15 lsb full-scale tempco i out(ref) = 0, internal reference, 0 c t a 70 c 15 10 ppm/ c i out(ref) = 0, internal reference, C 40 c t a 85 c 20 ppm/ c i out(ref) = 0, external reference 5 1 ppm/ c cc hara terist ics co u verter ltc1417acgn LTC1417CGN ltc1417aign ltc1417ign gn part marking consult factory for military grade parts. 1417a 1417 1417ai 1417i gn package 16-lead (narrow) plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 a in + a in v ref refcomp agnd extclkin sclk clkout v dd v ss busy convst rd shdn dgnd d out the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. specifications are measured while using the internal reference unless otherwise noted. (notes 5, 6) symbol parameter conditions min typ max units v in analog input range (note 9) 4.75v v dd 5.25v (unipolar) l 0 to 4.096 v 4.75v v dd 5.25v, C 5.25v v ss C 4.75v (bipolar) l 2.048 v i in analog input leakage current convst = high l 1 m a the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) a alog i put u u
3 ltc1417 symbol parameter conditions min typ max units c in analog input capacitance between conversions (sample mode) 14 pf during conversions (hold mode) 3 pf t acq sample-and-hold acquisition time l 150 500 ns t ap sample-and-hold aperture time C1.5 ns t jitter sample-and-hold aperture time jitter 5 ps rms cmrr analog input common mode rejection ratio 0v < (a in + = a in C ) < 4.096v (unipolar) 65 db C 2.048v < (a in + = a in C ) < 2.048v (bipolar) 65 db symbol parameter conditions min typ max units s/(n + d) signal-to-(noise + distortion) ratio 100khz input signal l 79 81 db thd total harmonic distortion 100khz input signal, first five harmonics l C85 C95 db sfdr spurious free dynamic range 200khz input signal C 98 db imd intermodulation distortion f in1 = 97.3khz, f in2 = 104.6khz C 97 db full power bandwidth 10 mhz full linear bandwidth s/(n + d) 3 77db 0.8 mhz parameter conditions min typ max units v ref output voltage i out = 0 l 2.480 2.500 2.520 v v ref output tempco i out = 0, 0 c t a 70 c 10 ppm/ c i out = 0, C 40 c t a 85 c 20 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.05 lsb/v C 5.25v v ss C 4.75v 0.05 lsb/v v ref output resistance 0.1ma | i out | 0.1ma 8 k w symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 1.4 pf v oh high level output voltage v dd = 4.75v, i o = C 10 m a 4.74 v v dd = 4.75v, i o = C 200 m a l 4.0 v v ol low level output voltage v dd = 4.75v, i o = 160 m a 0.05 v v dd = 4.75v, i o = C 1.6ma l 0.10 0.4 v i oz high-z output leakage d out , clkout v out = 0v to v dd , rd high l 10 m a c oz high-z output capacitance d out , clkout rd high (note 9) l 15 pf i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) a alog i put u u the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) dy a ic accuracy u w i ter al refere ce characteristics uu u digital i puts a d digital outputs u u the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5)
4 ltc1417 symbol parameter conditions min typ max units f sample(max) maximum sampling frequency l 400 khz t conv conversion time l 1.8 2.25 m s t acq acquisition time l 150 500 ns t acq + t conv acquisition plus conversion time l 2.1 2.5 m s t 1 shdn - to convst wake-up time from nap mode (note 10) 500 ns t 2 convst low time (notes 10, 11) l 40 ns t 3 convst to busy delay c l = 25pf l 35 70 ns t 4 data ready before busy - c l = 25pf l 712 ns t 5 delay between conversions (note 10) l 250 ns t 6 wait time rd after busy - l C5 ns t 7 data access time after rd c l = 25pf 15 30 ns l 40 ns c l = 100pf 20 40 ns l 55 ns t 8 bus relinquish time l 35 ns t 9 rd low time l t 7 ns t 10 convst high time l 40 ns t 11 delay time, sclk to d out valid c l = 25pf l 15 40 ns t 12 time from previous data remain valid after sclk c l = 25pf l 510 ns f sclk shift clock frequency (note 13) l 0 20 mhz f extclkin external conversion clock frequency l 0.05 9 mhz t dextclkin delay time, convst to external conversion clock input (note 9) l 20 m s symbol parameter conditions min typ max units v dd positive supply voltage (notes 10, 11) 4.75 5.25 v v ss negative supply voltage (note 10) bipolar only (v ss = 0v for unipolar) C 4.75 C 5.25 v i dd positive supply current unipolar, rd high (note 5) l 4.0 5.5 ma bipolar, rd high (note 5) l 4.3 6.0 ma nap mode shdn = 0v, rd = 0v 750 m a sleep mode shdn = 0v, rd = 5v 0.1 m a i ss negative supply current bipolar, rd high (note 5) l 2.0 2.8 ma nap mode shdn = 0v, rd = 0v 0.7 m a sleep mode shdn = 0v, rd = 5v 1.5 na p dis power dissipation unipolar l 20.0 27.5 mw bipolar l 31.5 44 mw power require e ts w u the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ti i g characteristics u w
5 ltc1417 symbol parameter conditions min typ max units t h sclk sclk high time (note 9) l 10 ns t l sclk sclk low time (note 9) l 10 ns t h extclkin extclkin high time l 0.04 20 m s t l extclkin extclkin low time l 0.04 20 m s note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together (unless otherwise noted). note 3: when these pin voltages are taken below v ss or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma without latchup if the pin is driven below v ss (ground for unipolar mode) or above v dd . note 4: when these pin voltages are taken below v ss they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, v ss = C 5v, f sample = 400khz, t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for a single- ended a in + input with a in C grounded. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: the falling convst edge starts a conversion. if convst returns high at a critical point during the conversion it can create small errors. for best results ensure that convst returns high either within 625ns after conversion start or after busy rises. note 12: typical rms noise at the code transitions. see figure 2 for histogram. note 13: t 11 of 40ns maximum allows f sclk up to 10mhz for rising capture with 50% duty cycle. f sclk up to 20mhz for falling capture with 5ns setup time. ti i g characteristics u w the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) typical perfor a ce characteristics uw typical inl curve differential nonlinearity vs output code s/(n + d) vs input frequency and amplitude
6 ltc1417 typical perfor a ce characteristics uw signal-to-noise ratio vs input frequency distortion vs input frequency spurious-free dynamic range vs input frequency input frequency (khz) 1 ?20 amplitude (db below the fundamental) ?00 ?0 ?0 ?0 0 10 100 thd 2nd 3rd 1417 g05 1000 ?0 nonaveraged, 4096 point fft, input frequency = 10khz nonaveraged, 4096 point fft, input frequency = 200khz intermodulation distortion plot frequency (khz) 0 120 amplitude (db) 100 ?0 ?0 ?0 40 100 140 200 1417 g09 ?0 0 20 60 80 120 160 180 f sample = 400khz f in1 = 97.303466khz f in2 = 104.632568khz v in = 4.096v p-p input offset voltage shift vs source resistance input common mode rejection vs input frequency power supply feedthrough vs ripple frequency input frequency (khz) 1 70 60 50 40 30 20 10 0 1417 g11 10 100 1000 common mode rejection (db) (t a = 25 c) input frequency (hz) signal-to-noise ratio (db) 1k 0 90 80 70 60 50 40 30 20 10 1417 g04 100k 1m 10k input frequency (hz) 1k 120 spurious free dynamic range (db) ?0 ?0 0 10k 100k 1m 1417 g06 ?0 ?0 100 frequency (khz) 0 100 50 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 150 1417 g07 200 f sample = 400khz f in = 10.05859375khz sfdr = 97.44db sinad = 81.71db frequency (khz) 0 50 100 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 150 1417 g08 200 f sample = 400khz f in = 197.949188khz sfdr = 98db sinad = 81.1db ripple frequency (hz) 1k feedthrough (db) 10k 100k 1417 g10 1m 10m 0 20 40 60 80 100 120 v ss v dd dgnd v ripple = 60mv f sample = 400khz f in = 200khz input source resistance ( ) 110 4 change in offset votlage (lsb) 5 6 7 8 100 1k 10k 100k 1m 1417 g12 3 2 1 0 9 10
7 ltc1417 typical perfor a ce characteristics uw v dd supply current vs temperature (unipolar mode) a in + (pin 1): positive analog input. a in C (pin 2): negative analog input. v ref (pin 3): 2.50v reference output. bypass to agnd with 1 m f. refcomp (pin 4): 4.096v reference output. bypass to agnd using 10 m f tantalum in parallel with 0.1 m f ceramic. agnd (pin 5): analog ground. extclkin (pin 6): external conversion clock input. a 5v input will enable the internal conversion clock. sclk (pin 7): data clock input. clkout (pin 8): conversion clock output. d out (pin 9): serial data output. dgnd (pin 10): digital ground. shdn (pin 11): power shutdown input. low selects shutdown. shutdown mode selected by rd. rd = 0v for nap mode and rd = 5v for sleep mode. rd (pin 12): read input. this enables the output drivers. rd also sets the shutdown mode when shdn goes low. rd and shdn low selects the quick wake-up nap mode, rd high and shdn low selects sleep mode. v dd supply current vs sampling frequency (unipolar mode) v dd supply current vs temperature (bipolar mode) v dd supply current vs sampling frequency (bipolar mode) v ss supply current vs temperature (bipolar mode) v ss supply current vs sampling frequency (bipolar mode) pi n fu n ctio n s uuu (t a = 25 c) temperature ( c) ?5 v dd supply current (ma) 75 6 5 4 3 2 1 0 1417 g13 ?0 150 ?5 0 25 50 100 125 temperature ( c) ?5 v dd supply current (ma) 75 6 5 4 3 2 1 0 1417 g14 ?0 150 ?5 0 25 50 100 125 temperature ( c) ?5 v ss supply current (ma) 75 3.0 2.5 2.0 1.5 1.0 0.5 0 1417 g15 ?0 150 ?5 0 25 50 100 125 sampling frequency (khz) 050 v dd supply current (ma) 3.0 4.0 5.0 400 450 1417 g16 2.0 1.0 2.5 3.5 4.5 1.5 0.5 0 100 200 150 300 350 250 500 sampling frequency (khz) 050 v dd supply current (ma) 3.0 4.0 5.0 400 450 1417 g17 2.0 1.0 2.5 3.5 4.5 1.5 0.5 0 100 200 150 300 350 250 500 sampling frequency (khz) 050 v ss supply current (ma) 1.5 2.0 2.5 400 450 1417 g18 1.0 0.5 0 100 200 150 300 350 250 500
8 ltc1417 load circuits for access timing load circuits for output float delay convst (pin 13): conversion start signal. this active low signal starts a conversion on its falling edge. busy (pin 14): the busy output shows the converter status. it is low when a conversion is in progress. v ss (pin 15): negative supply, C5v for bipolar operation. bypass to agnd using 10 m f tantalum in parallel with 0.1 m f ceramic. analog ground for unipolar operation. v dd (pin 16): 5v positive supply. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f ceramic. pi n fu n ctio n s uuu test circuits fu n ctio n al block diagra uu w 1k c l d out dgnd a) hi-z to v oh and v ol to v oh c l d out 1k 5v b) hi-z to v ol and v oh to v ol dgnd 1417 tc01 1k 30pf d out a) v oh to hi-z 30pf d out 1k 5v b) v ol to hi-z 1417 tc02 14-bit capacitive dac comp ref amp 2.5v ref 8k refcomp (4.096v) c sample c sample d out busy control logic convst rd clkout shdn internal clock extclkin mux zeroing switches sclk v dd 16 15 9 7 14 8 12 13 11 6 10 5 4 3 2 1 a in + a in v ref agnd dgnd 14 1417 bd + successive approximation register v ss (0v for unipolar mode ?v for bipolar mode) shift register
9 ltc1417 conversion details the ltc1417 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit serial output. the adc is com- plete with a precision reference and an internal clock. the control logic provides easy interface to microprocessors and dsps (please refer to digital interface section for the data format). conversion start is controlled by the convst input. at the start of the conversion, the successive approximation register (sar) is reset. once a conversion cycle has begun, it cannot be restarted. during the conversion, the internal differential 14-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the a in + and a in C inputs are con- nected to the sample-and-hold capacitors (c sample ) dur- ing the acquire phase and the comparator offset is nulled by the zeroing switches. in this acquire phase, a minimum delay of 500ns will provide enough time for the sample- and-hold capacitors to acquire the analog signal. during the convert phase, the comparator zeroing switches open, placing the comparator in compare mode. the input switches connect the c sample capacitors to ground, transferring the differential analog input charge onto the summing junction. this input charge is successively compared with the binary weighted charges supplied by the differential capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the differential dac output balances the a in + and a in C input charges. the sar contents (a 14-bit data word) that represent the difference of a in + and a in C are output through the serial pin d out . dc performance one way of measuring the transition noise associated with a high resolution adc is to use a technique where a dc signal is applied to the input of the adc and the resulting output codes are collected over a large number of conver- sions. for example in figure 2, the distribution of output code is shown for a dc input that has been digitized 4096 times. the distribution is gaussian and the rms code transition is about 0.33lsb. figure 1. simplified block diagram 1417 f01 shift register sar c dac + c dac v dac v dac + + comp d out 14 hold hold hold a in + a in zeroing switches c sample c sample + hold sample sample applicatio n s i n for m atio n wu u u code ? counts 1500 2000 2500 1 1417 f02 1000 500 0 ? 0 2 3000 3500 4000 figure 2. histogram for 4096 conversions dynamic performance the ltc1417 has excellent high speed sampling capabil- ity. fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise performance at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies beyond the fundamental. figure 3 shows a typical ltc1417 fft plot.
10 ltc1417 signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 3b shows a typical spectral content with a 400khz sampling rate and a 200khz input. the dynamic performance is excellent for input frequencies up to and beyond the nyquist limit of 200khz. figure 4. effective bits and signal/(noise + distortion) vs input frequency applicatio n s i n for m atio n wu u u figure 3a. ltc1417 nonaveraged, 4096 point fft, input frequency = 10khz figure 3b. ltc1417 nonaveraged, 4096 point fft, input frequency = 200khz frequency (khz) 0 100 50 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 150 1417 g07 200 f sample = 400khz f in = 10.05859375khz sfdr = 97.44db sinad = 81.71db frequency (khz) 0 50 100 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 150 1417 g08 200 f sample = 400khz f in = 197.949188khz sfdr = 98db sinad = 81.1db effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: enob (n) = [s/(n + d) C 1.76]/6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 400khz, the ltc1417 maintains near ideal enobs up to the nyquist input frequency of 200khz (refer to figure 4). input frequency (hz) 4 effective bits s/(n + d) (db) 6 8 10 12 10k 100k 1m 1417 ta02 2 1k 14 86 80 74 68 62 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd log vvv vn v = +++ 20 234 1 222 2 ... where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 5. the ltc1417 has good distortion performance up to the nyquist frequency and beyond.
11 ltc1417 intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, 2nd order imd terms include (fa fb). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd-order imd products can be expressed by the following formula: imd fa fb log amplitude + () = () 20 at fa fb amplitude at fa peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full-power and full-linear bandwidth the full-power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db from a full-scale input signal. the full-linear bandwidth is the input frequency at which the s/(n + d) has dropped to 77db (12.5 effective bits). the ltc1417 has been designed to optimize input band- width, allowing the adc to undersample input signals with frequencies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far beyond nyquist. driving the analog input the differential analog inputs of the ltc1417 are easy to drive. the inputs may be driven differentially or as a single- ended input (i.e., the a in C input is grounded). the a in + and a in C inputs are sampled at the same instant. any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sample- and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, then the ltc1417 inputs can be driven directly. as source impedance increases, so will acquisition time (see figure 7). for minimum acquisition time, with high source impedance, a buffer amplifier must be used. the only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts 500ns for full throughput rate. applicatio n s i n for m atio n wu u u figure 5. distortion vs input frequency input frequency (khz) 1 ?20 amplitude (db below the fundamental) ?00 ?0 ?0 ?0 0 10 100 thd 2nd 3rd 1417 g05 1000 ?0 figure 6. intermodulation distortion plot frequency (khz) 0 120 amplitude (db) 100 ?0 ?0 ?0 40 100 140 200 1417 g09 ?0 0 20 60 80 120 160 180 f sample = 400khz f in1 = 97.303466khz f in2 = 104.632568khz v in = 4.096v p-p
12 ltc1417 lt1360: 50mhz voltage feedback amplifier. 3.8ma sup- ply current, 2.5v to 15v supplies. high a vol , 1mv offset and 80ns settling to 1mv (4v step, inverting and noninverting configurations) make it suitable for fast dc applications. excellent ac specifications. dual and quad versions are available as lt1361 and lt1362. lt1468: 90mhz voltage feedback amplifier. 5v to 15v supplies. lower distortion and noise. settles to 0.01% in 770ns. distortion is C115db to 20khz. lt1498/lt1499: 10mhz, 6v/ m s, dual/quad rail-to-rail input and output op amps. 1.7ma supply current per amplifier. 2.2v to 15v supplies. good ac performance, input noise voltage = 12nv/ ? hz (typ). lt1630/lt1631: 30mhz, 10v/ m s, dual/quad rail-to-rail input and output precision op amps. 3.5ma supply current per amplifier. 2.7v to 15v supplies. best ac performance, input noise voltage = 6nv/ ? hz (typ), thd = C 86db at 100khz. lt1813: dual 100mhz 750v/ m s 3ma vfa. 5v to 5v supplies. distortion is C 86db to 100khz and C 77db to 1mhz with 5v supplies (2v p-p into 500 w ). great part for fast ac applications with 5v supplies. input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1417 noise and distortion. the small-signal band- width of the sample-and-hold circuit is 10mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for example, figure 8 shows a 1000pf applicatio n s i n for m atio n wu u u linearview is a trademark of linear technology corporation. figure 7. t acq vs source resistance source resistance ( ) 0.1 acquisition time ( s) 10 1 1 100 1k 10k 1417 f07 0.01 10 100 100k choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, choose an amplifier that has a low output impedance (<100 w ) at the closed-loop bandwidth frequency. for example, if an amplifier is used in a gain of 1 and has a closed-loop bandwidth of 10mhz, then the output impedance at 10mhz must be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 10mhz to ensure ad- equate small-signal settling for full throughput rate. if slower op amps are used, more settling time can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc1417 will depend on the application. generally, applications fall into two categories: ac applications where dynamic specifica- tions are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc1417. more detailed information is available in the linear technology databooks and on the linearview tm cd-rom. lt ? 1354: 12mhz, 400v/ m s op amp. 1.25ma maximum supply current. good ac and dc specifications. suitable for dual supply application. lt1357: 25mhz, 600v/ m s op amp. 2.5ma maximum supply current. good ac and dc specifications. suitable for dual supply application. figure 8. rc input filter ltc1417 a in + a in v ref refcomp agnd analog input 100 1417 f08 1 2 3 4 5 1000pf 10 m f
13 ltc1417 applicatio n s i n for m atio n wu u u capacitor from + a in to ground and a 100 w source resistor to limit the input bandwidth to 1.6mhz. the 1000pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sam- pling glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. input range the 2.048v and 0v to 4.096v input ranges of the ltc1417 are optimized for low noise and low distortion. most op amps also perform well over these ranges, allowing direct coupling to the analog inputs and eliminat- ing the need for special translation circuitry. some applications may require other input ranges. the ltc1417 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. the following sections describe the reference and input circuitry and how they affect the input range. internal reference the ltc1417 has an on-chip, temperature compensated, curvature corrected, bandgap reference which is factory trimmed to 2.500v. it is internally connected to a reference amplifier and is available at pin 3. an 8k resistor is in series with the output so that it can be easily overdriven in applications where an external reference is required, see figure 9. a capacitor must be connected between the reference amplifier compensation pin (refcomp, pin 4) and ground. the reference is stable with capacitors of 1 m f or greater. for the best noise performance, a 10 m f in parallel with a 0.1 m f ceramic is recommended. the v ref pin can be driven with a dac or other means to provide input span adjustment. the reference should be kept in the range of 2.25v to 2.75v for specified linearity. unipolar / bipolar operation and adjustment figure 10a shows the input/output characteristics for the ltc1417. the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, fs C 1.5lsb). the output code is natural binary with 1lsb = fs/16384 = 4.096v/16384 = 250 m v. figure 10b shows the input/output transfer characteristics for the bipolar mode in twos complement format. figure 9. using the lt1460 as an external reference analog input 5v 1417 f09 10 m f 2.5v 0.1 m f v in v out lt1460-2.5 1 2 3 4 5 ltc1417 5v a in + a in v ref refcomp agnd v dd figure 10a. ltc1417 unipolar transfer characteristics figure 10b. ltc1417 bipolar transfer characteristics input voltage (v) 0v output code fs ?1lsb 1417 f10a 111...111 111...110 111...101 111...100 000...000 000...001 000...010 000...011 1 lsb unipolar zero 1lsb = fs 16384 4.096v 16384 = input voltage (v) 0v output code ? lsb 1417 f10b 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 ?1lsb fs/2 fs = 4.096v 1lsb = fs/16384
14 ltc1417 applicatio n s i n for m atio n wu u u figure 11b. offset and full-scale adjust circuit if C 5v is available figure 11a. offset and full-scale adjust circuit if C 5v is not available r2 50k analog input 1417 f11a 5v r4 100 w r3 24k r7 48k r6 24k r1 50k r5 47k 0.1 m f 10 m f r8 100 w 1 2 3 4 5 ltc1417 a in + a in v ref refcomp agnd v ss v dd offset adj fs adj analog input 1417 f11b 5v ?v ?v r4 100 w r2 50k fs adj offset adj r3 24k r6 24k r1 50k r5 47k 0.1 m f 10 m f 1 2 3 4 5 ltc1417 a in + a in v ref refcomp agnd v ss v dd unipolar offset and full-scale error adjustment in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figures 11a and 11b show the extra components required for full- scale error adjustment. zero offset is achieved by adjust- ing the offset applied to the a in C input. for zero offset error, apply 125 m v (i.e., 0.5lsb) at the input and adjust the offset at the a in C input until the output code flickers between 0000 0000 0000 00 and 0000 0000 0000 01. for full-scale adjustment, an input voltage of 4.095625v (fs C 1.5lsbs) is applied to a in + and r2 is adjusted until the output code flickers between 1111 1111 1111 10 and 1111 1111 1111 11. bipolar offset and full-scale error adjustment bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case using the circuit in figure 11b. again, bipolar offset error must be adjusted before full-scale error. bipolar offset error adjustment is achieved by adjusting the offset applied to the a in C input. for zero offset error, apply C 125 m v (i.e., C 0.5lsb) at a in + and adjust the offset at the a in C input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. for full-scale adjustment, an input voltage of 2.047625v (fs C 1.5lsbs) is applied to a in + and r2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. board layout and grounding to obtain the best performance from the ltc1417, a printed circuit board with ground plane is required. the ground plane under the adc area should be as free of breaks and holes as possible, such that a low impedance path between all adc grounds and all adc decoupling capacitors is provided. it is critical to prevent digital noise from being coupled to the analog input, reference or analog power supply lines. layout should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track. an analog ground plane separate from the logic system ground should be established under and around the adc. pin 5 (agnd) and pin 10 (dgnd) and all other analog grounds should be connected to this single analog ground plane. the refcomp bypass capacitor and the v dd by- pass capacitor should also be connected to this analog ground plane. no other digital grounds should be con- nected to this analog ground plane. low impedance ana- log and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation comparator. the problem can be eliminated by forcing the microprocessor into a
15 ltc1417 wait state during conversion or by using three-state buff- ers to isolate the adc data bus. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc1417 has differential inputs to minimize noise coupling. common mode noise on the a in + and a in C leads will be rejected by the input cmrr. the a in C input can be used as a ground sense for the a in + input; the ltc1417 will hold and convert the difference voltage between a in + and a in C . the leads to a in + (pin 1) and a in C (pin 2) should be kept as short as possible. in applications where this is not possible, the a in + and a in C traces should be run side by side to equalize coupling. supply bypassing high quality, low series resistance ceramic, 10 m f bypass capacitors should be used at the v dd and refcomp pins. surface mount ceramic capacitors such as taiyo yuden lmk325bj106mn provide excellent bypassing in a small board space. alternatively 10 m f tantalum capacitors in parallel with 0.1 m f ceramic capacitors can be used. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. applicatio n s i n for m atio n wu u u example layout figures 13a, 13b, 13c and 13d show the schematic and layout of a suggested evaluation board. the layout demon- strates the proper use of decoupling capacitors and ground plane with a 2-layer printed circuit board. power shutdown the ltc1417 provides two power shutdown modes, nap and sleep, to save power during inactive periods. the nap mode reduces adc power dissipation by 80% and leaves only the digital logic and reference powered up. the wake-up time from nap to active is 500ns (see figure 14). in sleep mode, all bias currents are shut down and only leakage current remains about 2 m a. wake-up time from sleep mode is much slower since the reference circuit must power up and settle to 0.005% for full 14-bit accuracy. sleep mode wake-up time is dependent on the value of the capacitor connected to the refcomp (pin 4). the wake-up time is 30ms with the recommended 10 m f capacitor. shutdown is controlled by pin 11 (shdn); the adc is in shutdown when it is low. the shutdown mode is selected with pin 12 (rd); low selects nap mode, high selects sleep mode. figure 12. power supply grounding practice 1417 f12 digital system analog input circuitry 5 4 2 15 16 10 1 10 f 3 1 f10 f 10 f analog ground plane + a in + agnd refcomp v ss v ref v dd ltc1417 dgnd a in figure 14. shdn to convst wake-up timing t 1 shdn convst 1417 f14
16 ltc1417 applicatio n s i n for m atio n wu u u figure 13b. suggested evaluation circuit boardcomponent side silkscreen figure 13c. suggested evaluation circuit boardcomponent side figure 13d. suggested evaluation circuit boardsolder side figure 13a. suggested evaluation circuit schematic + +a in ? in v ref refcomp agnd extclkin sck clkout v dd v ss busy convst rd shdn dgnd d out 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 u1 LTC1417CGN ?a 5a 5a jp7 c8 10 f 16v c7 10 f 16v c6 1 f jp3 jp2 jp5a jp6 5a j8 con7 j3 bnc jp4 5a r5 100k jp5b jp5c jp1 c3 1000pf 50v r2 10k r1 10k j1 bnc j2 bnc r4 75 r3 75 + u3 lt1363cn8 c4 0.1 f c5 0.1 f 3 7 4 8 1 5 optional 66 2 + u4 lt1363cs8 3 7 4 8 1 5 2 5a c1 0.1 f c2 0.1 f c12 0.1 f bypass capacitor for u2 5a 18 u2a tc74hct244af 2 19 1 + c9 10 f 16v e3 ?v ?a c11 10 f 16v + + 17 u2b 3 19 1 15 u2d 5 19 1 13 u2f 7 19 1 11 u2h 9 19 1 16 u2c 4 19 1 14 u2e 6 19 1 12 u2g 8 19 1 1 2 3 4 5 6 7 busy rd sclk clkout extclkin r8 100k r6 100k r7 100k 1417 f13a e1 5v 5a agnd dgnd c10 10 f 16v + e2 gnd d out
17 ltc1417 digital interface the ltc1417 operates in serial mode. the rd control input is common to all peripheral memory interfacing. only four digital interface lines are required, sclk, convst, extclkin and d out . sclk, the serial data shift clock can be an external input or supplied by the ltc1417s internal clock. internal clock the adc has an internal clock. either the internal clock or an external clock may be used as the conversion clock (see figure 15). the internal clock is factory trimmed to achieve a typical conversion time of 1.8 m s, and a maximum con- version time over the full operating temperature range of 2.5 m s. no external adjustments are required, and with the guaranteed maximum acquisition time of 0.5 m s, through- put performance of 400ksps is assured. conversion control conversion start is controlled by the signal applied to the convst input. a falling edge on the signal applied to the convst pin starts a conversion. once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output. busy is low during a conversion. data output output will be active when rd is low. a high rd will three- state the ouput. in unipolar mode (v ss = 0v), the data will be in straight binary format (corresponding to the unipolar input range). in bipolar mode (v ss = C 5v), the data will be in twos complement format (corresponding to the bipolar input range). serial output mode conversions are started by a falling convst edge. after a conversion is completed and the output shift register has been updated, busy will go high and valid data will be available on d out (pin 9). this data can be clocked out either before the next conversion starts or it can be clocked out during the next conversion. to enable the serial data output buffer and shift clock, rd must be low. figure 15 shows a function block diagram of the ltc1417. there are two pieces to this circuitry: the conversion clock selection circuit (extclkin and clkout) and the serial port (sclk, d out and rd). applicatio n s i n for m atio n wu u u three state buffer three state buffer 12 rd 7 ?? sclk extclkin 6 busy 1417 f15 d out 9 clkout 8 14 shift register internal clock clock detector 16 conversion clock cycles eoc data in 14 data out clock input ?? sar figure 15. functional block diagram
18 ltc1417 conversion clock selection in figure 15, the conversion clock controls the internal adc operation. the conversion clock can be either inter- nal or external. by connecting extclkin high, the inter- nal clock is selected. this clock generates 16 clock cycles which feed into the sar for each conversion. to select an external conversion clock, apply an external conversion clock to extclkin (pin 6). (when an external shift clock (sclk) is used during a conversion, the sclk should be used as the external conversion clock to avoid the noise generated by the asynchronous clocks. to maintain accuracy, the external conversion clock fre- quency must be between 50khz and 9mhz.) the sar sends an end of conversion signal, eoc, that gates the external conversion clock so that only 16 clock cycles can go into the sar, even if the external clock, extclkin, contains more than 16 cycles. when rd is low, these 16 cycles of conversion clock (whether internally or externally generated) will appear on clkout during each conversion and then clkout will remain low until the next conversion. if desired, clkout can be used as a master clock to drive the serial port. because clkout is running during the conversion, it is important to avoid excessive loading that can cause large supply transients and create noise. for the best performance, limit clkout loading to 20pf. serial port the serial port in figure 15 is made up of a 16-bit shift register and a three-state output buffer that are con- trolled by two inputs: sclk and rd. the serial port has one output, d out , that provides the serial output data. the sclk is used to clock the shift register. data may be clocked out with the internal conversion clock operating as a master by connecting clkout (pin 8) to sclk (pin 7) or with an external data clock applied to sclk. the minimum number of sclk cycles required to trans- fer a data word is 14. normally, sclk contains 16 clock cycles for a word length of 16 bits; 14 bits with msb first, followed by two trailing zeros. a logic high on rd disables sclk and three-states d out . in case of using a continuous sclk, rd can be controlled to limit the number of shift clocks to the desired number (i.e., 16 cycles) and to three-state d out after the data transfer. in power shutdown mode (shdn = low), a high rd selects sleep mode while a low rd selects nap mode. d out outputs the serial data; 14 bits, msb first, on the falling edge of each sclk (see figures 16 and 17). if 16 sclks are provided, the 14 data bits will be followed by two zeros. the msb (d13) will be valid on the first rising and the first falling edge of the sclk. d12 will be valid on the second rising and the second falling edge as will all the remaining bits. the data may be captured using either edge. the largest hold time margin is achieved if data is captured on the rising edge of sclk. busy gives the end-of-conversion indication. when the ltc1417 is configured as a serial bus master, busy can be used as a framing pulse. to three-state the serial port after transferring the serial output data, busy and rd should be connected together at the adc (see figure 17). figures 17 to 20 show several serial modes of operation, demonstrating the flexibility of the ltc1417 serial interface. applicatio n s i n for m atio n wu u u figure 16. sclk to d out delay t 12 t 11 sclk v il v oh v ol d out 1417 f16
19 ltc1417 applicatio n s i n for m atio n wu u u figure 17. internal conversion clock selected. data transferred during conversion using the adc clock output as a master shift clock (sclk driven from clkout) d12 d11 d11 d12 capture on rising clock d13 d10d9d8d7d6d5d4d3d2d1d0 fill zeros d13 1 t 2 t 3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 d13 d13 d12 d11 hi-z hi-z data n data (n ?1) (sample n) (sample n + 1) d out extclkin = 5 clkout (= sclk) convst t 10 t conv t 5 sample hold hold t 7 t 4 t 8 1417 f17 busy (= rd) t 12 t 11 clkout (= sclk) v il v oh v ol d out capture on falling clock ltc1417 busy (= rd) clkout ( = sclk) busy convst convst rd sclk clkout d out 14 13 12 7 8 9 d out m p or dsp (configured as slave) or shift register serial data output during a conversion using internal clock for conversion and data transfer . figure 17 shows data from the previous conversion being clocked out during the conversion with the ltc1417 internal clock providing both the conversion clock and the sclk. the internal clock has been optimized for the fastest conversion time; consequently, this mode can provide the best overall speed performance. to select the internal conversion clock, tie extclkin (pin 6) high. the internal clock appears on clkout (pin 8) which can be tied to sclk (pin 7) to supply the sclk.
20 ltc1417 using external clock for conversion and data transfer . in figure 18, data from the previous conversion is output during the conversion with an external clock providing both the conversion clock and the shift clock. to select an external conversion clock, apply the clock to extclkin. the same clock is also applied to sclk to provide a data applicatio n s i n for m atio n wu u u figure 18. external conversion clock selected. data transferred during conversion using the external clock (external clock drives both extclkin and sclk) shift clock. to maintain conversion accuracy, the external clock frequency must be between 50khz and 9mhz. using an external clock to transfer data while an internal clock controls the conversion process is not recom- mended. as both signals are asynchronous, clock noise can corrupt the conversion result. d12 d11 d11 d12 capture on rising clock d13 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 fill zeros d13 1 t 2 t 3 t 7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 d13 d13 d12 d11 hi-z hi-z data n data (n ?1) (sample n) (sample n + 1) d out extclkin (= sclk) convst t 10 t conv t 5 sample hold hold t dextclkin t 4 t 8 1417 f18 busy (= rd) t 12 t 11 t lextclkin t hextclkin extclkin (= sclk) v il v oh v ol d out capture on falling clock ltc1417 busy (= rd) extclkin ( = sclk) busy convst convst rd extclkin sclk d out d out 9 14 13 7 6 12 m p or dsp
21 ltc1417 1211109876543210 fill zeros d13 t 2 t 3 12345678910111213141516 hi-z data n hi-z (sample n) d out extclkin = 5 convst t 10 t conv t 5 hold sample t 6 t 7 t 9 1417 f19 t 8 busy sclk rd d11 d12 capture on rising clock d13 t 12 t 11 t lsclk t hsclk sclk v il v oh v ol d out capture on falling clock ltc1417 busy convst 14 13 9 12 7 convst rd sclk d out m p or dsp int c0 sck miso applicatio n s i n for m atio n wu u u figure 19. internal conversion clock selected. data transferred after conversion using an external sclk. busy - indicates end of conversion microwire is a trademark of national semiconductor corporation. serial data output after a conversion using an internal conversion clock and an external data clock . in this mode, data is output after the end of each conversion and before the next conversion is started (figure 19). the internal clock is used as the conversion clock and an external clock is used for the sclk. this mode is useful in applications where the processor acts as a serial bus master device. this mode is spi and microwire tm compatible. it also allows operation when the sclk frequency is very low (less than 30khz). to select the internal conversion clock, tie extclkin high. the external sclk is applied to sclk. rd can be used to gate the external sclk, such that data will clock only after rd goes low and to three-state d out after data transfer. if more than 16 sclks are provided, more zeros will be filled in after the data word indefinitely.
22 ltc1417 t 2 t 3 12345678910111213141516 convst extclkin t 10 t dextclkin t 5 hold sample t 6 t 4 t 9 t 8 busy sclk rd 12345678910111213141516 1 2 34 1211109876543210 fill zeros d13 hi-z data n hi-z (sample n) d out t conv t 7 1417 f20 d11 d12 capture on rising clock d13 t 12 t 11 sclk v il v oh v ol d out capture on falling clock t lsclk t hsclk ltc1417 busy convst convst rd extclkin sclk d out 6 13 12 7 14 9 m p or dsp clkout int c0 sck miso applicatio n s i n for m atio n wu u u figure 20. external conversion clock selected. data transferred after conversion using an external sclk. busy - indicates end of conversion using an external conversion clock and an external data clock . in figure 20, data is also output after each conversion is completed and before the next conversion is started. an external clock is used for the conversion clock and either another or the same external clock is used for the sclk. this mode is identical to figure 19 except that an external clock is used for the conversion. this mode allows the user to synchronize the a/d conversion to an external clock either to have precise control of the internal bit test timing or to provide a precise conversion time. as in figure 19, this mode works when the sclk frequency is very low (less than 30khz). however, the external conver- sion clock must be between 30khz and 9mhz to maintain accuracy. if more than 16 sclks are provided, more zeros will be filled in after the data word indefinitely. to select the external conversion clock, apply an external conversion clock to extclkin. the external sclk is applied to sclk. rd can be used to gate the external sclk such that data will be clocked out only after rd goes low.
23 ltc1417 typical applicatio n s u figure 21 shows the connections necessary for interfacing the ltc1417 and ltc1391 8-channel signal acquisition system to an spi port. with the sample software routine shown in listing a, the spi uses mosi to send serial data to the ltc1391 8-channel multiplexer, selecting one of eight mux channels. while data is sent to the ltc1391, spi uses miso to retrieve conversion data from the ltc1417. after the data transfer is complete, the conversion start signal is sent to the ltc1417. the end of conversion is signaled by a logic high on the busy output. when this occurs, data is exchanged between the ltc1417/ltc1391 and the controller. the timing diagram in figure 22 shows the relation be- tween mux channel selection data and the conversion data that are simultaneously exchanged. there is a two conversion delay between the mux data selects a given channel and when that channels data is retrieved. figure 21. 0v to 4.096v, 8-channel data acquisition system configured for control and data retrieval by a 68hc11 m c. code is shown in listing a 1417 f21 1 f 10 f 5v 10 f 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1417 5v 5v nc nc port c, bit 7 port c, bit 0 ss miso mc68hc11 clk mosi a in + a in v ref refcomp agnd extclkin sclk clkout v dd v ss busy convst rd shdn dgnd d out ltc1391 s0 s1 s2 s3 s4 s5 s6 s7 16 15 14 13 12 11 10 9 v + d v d out d in cs clk dgnd in1 in2 in3 in4 in5 in6 in7 in8 1 2 3 4 5 6 7 8 0.1 f
24 ltc1417 typical applicatio n s u *********************************************************************** * * * this example program retrieves data from a previous ltc1417 * * conversion and loads the next ltc1391 mux channel. it stores the * * 14-bit, right justified data in two consecutive memory locations. * * it finishes by initiating the next conversion. * * * *********************************************************************** * ************************************ * 68hc11 register definitions * ************************************ * pioc equ $1002 parallel i/o control register * staf,stai,cwom,hnds, oin, pls, ega,invb portc equ $1003 port c data register * bit7,bit6,bit5,bit4,bit3,bit2,bit1,bit0 ddrc equ $1007 port d data direction register * bit7,bit6,bit5,bit4,bit3,bit2,bit1,bit0 * 1 = output, 0 = input portd equ $1008 port d data register * - , - , ss* ,csk ;mosi,miso,txd ,rxd ddrd equ $1009 port d data direction register spcr equ $1028 spi control register * spie,spe ,dwom,mstr;spol,cpha,spr1,spr0 spsr equ $1029 spi status register * spif,wcol, - ,modf; - , - , - , - spdr equ $102a spi data register; read-buffer; write-shifter * * ram variables to hold the ltc1417s 14 conversion result * din1 equ $00 this memory location holds the ltc1417s bits 13 - 08 din2 equ $01 this memory location holds the ltc1417s bits 07 - 00 mux equ $02 this memory location holds the mux address data * ******************************************* * start getdata routine * ******************************************* * org $c000 program start location init1 ldaa #$03 0,0,0,0,0,0,1,1 * staf=0,stai=0,cwom=0,hnds=0, oin=0, pls=0, ega=1,invb=1 staa pioc ensures that the pioc registers status is the same * as after a reset, necessary of simple port d manipulation ldaa #$01 0,0,0,0,0,0,0,1 * bit7=input,- ,- ,- ,- ,- ,- ,bit0=output * bit7 used for busy signal input, bit0 used for convst * signal output staa ddrc the direction of portds bits are now set ldaa portc get contents of port c oraa #%00000001 set bit0 high staa portc initialize convst to a logic high ldaa #$2f -,-,1,0;1,1,1,1 * -, -, ss*-hi, sck-lo, mosi-hi, miso-hi, x, x staa portd keeps ss* a logic high when ddrd, bit 5 is set ldaa #$38 -,-,1,1;1,0,0,0 staa ddrd ss* , sck, mosi are configured as outputs * miso, txd, rxd are configured as inputs * ddrds bit 5 is a 1 so that port ds ss* pin is a general output ldaa #$50 staa spcr the spi is configured as master, cpha = 0, cpol = 0 * and the clock rate is e/2 listing a
25 ltc1417 * (this assumes an e-clock frequency of 4mhz. for higher * e-clock frequencies, change the above value of $50 to a * value that ensures the sck frequency is 2mhz or less.) getdatapshx pshy psha * ***************************************** * setup indecies * ***************************************** * ldx #$0 the x register is used as a pointer to the memory * locations that hold the conversion data ldy #$1000 * ***************************************** * the next short loop ensures that the * * ltc1417s conversion is finished * * before starting the spi data transfer * ***************************************** * convendldaa portc retrieve the contents of port d anda #%10000000 look at bit7 * bit7 = hi; the ltc1417s conversion is complete * bit7 = lo; the ltc1417s conversion is not * complete bpl convend branch to the loops beginning while bit7 remains * low * ************************************************************************* * this routine sends data to the ltc1417 and sets its mux channel. the * * very first time this routine is entered produces invalid data. each * * time thereafter, the data will correspond to the previous active * * convst signal sent to the ltc1417. * ************************************************************************* * ldaa #$00 dummy value for upper byte of 16-bit spi transfer bclr portd,y %00100000 this sets the ss* output bit to a logic * low, selecting the ltc1417 staa spdr transfer accum. a contents to spi register to initiate * serial transfer waitmx1 ldaa spsr get spi transfer status bpl waitmx1if the transfer is not finished, read status ldaa spdr load accumulator a with the current byte of ltc1417 data * that was just received staa din1 transfer the ltc1417s high byte (bit13 - bit6) to memory ldaa mux retrieve mux address oraa #$08 set the muxs enable bit staa spdr transfer accum. a contents to spi register to initiate * serial transfer waitmx2 ldaa spsr get spi transfer status bpl waitmx2if the transfer is not finished, read status bset portd,y %00100000 this sets the ss* output bit to a logic * high, de-selecting the ltc1417 ldaa spdr load accumulator a with the current byte of ltc1417 data * that was just received staa din2 transfer the ltc1417s low byte (bit5 - bit0) to memory ldd din1 load the contents of din1 and din2 into the double * accumulator d lsrd lsrd two logical shifts to the right to right justify the * 14-bit conversion results std din1 place right justified result back in memory typical applicatio n s u
26 ltc1417 * ***************************************** * initiate a ltc1417 conversion * ***************************************** * bclr portc,y %00000001 this sets portc, bit0 output to a logic * low, initiating a conversion bset portc,y %00000001 this resets portc, bit0 output to a logic * high, returning convst to a logic high * pula restore the a register puly restore the y register pulx restore the x register rts typical applicatio n s u figure 22. this diagram shows the relationship between the selected ltc1391 mux channel and the conversion data retrieved from the ltc1417 when using the sample program in listing a. at any point in time, a two conversion delay exists between the selected mux channel and when its data is retrieved convst busy rd mux data adc data mux out ch5 ch4 ch3 ch2 ch1 ch3 ch2 ch1 ch0 ch7 ch0 ch1 ch2 ch3 ch4 1417 f22
27 ltc1417 typical applicatio n s u figure 23 uses the dg408 to select one of eight 2.048v bipolar signals and apply it to the ltc1417s analog input. the circuit is designed to connect to a 68hc11 m c. the muxs parallel input is connected to the controllers port c and the ltc1417s serial interface is accessed through the controllers spi interface. the sequence to generate a conversion is shown in sample program listing b. the first step selects a mux channel. this is followed by initiating a conversion and waiting for busy to go high, signifying end of conversion. once busy goes low, the spi is used to retrieve the 14-bit conversion data. the timing relationships between the various control signals and data transmission are shown in figure 24. figure 23. with an input range of 2.048v for each of eight inputs, this data acquisition system is configured for communication with the 68hc11 m c 1417 f23 1 f 10 f 5v nc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1417 5v 5v 5v 5v port c, bit 7 port c, bit 6 port c, bit 2 port c, bit 1 port c, bit 0 ss miso clk a in + a in v ref refcomp agnd extclkin sclk clkout v dd v ss busy convst rd shdn dgnd d out dg408 s1 s2 s3 s4 s5 s6 s7 s8 13 3 14 2 v + v gnd en a2 a1 a0 d in1 in2 in3 in4 in5 in6 in7 in8 1 2 3 4 5 6 7 8 0.1 f 0.1 f mc68hc11
28 ltc1417 typical applicatio n s u listing b ************************************************************************* * * * this example program selects a dg408 mux channel using parallel * * port c, initiates a conversion, and retrieves data from the ltc1417. * * it stores the 14-bit, right justified data in two consecutive memory * * locations. * * * ************************************************************************* * ***************************************** * 68hc11 register definitions * ***************************************** * pioc equ $1002 parallel i/o control register * staf,stai,cwom,hnds, oin, pls, ega,invb portc equ $1003 port c data register * bit7,bit6,bit5,bit4,bit3,bit2,bit1,bit0 ddrc equ $1007 port d data direction register * bit7,bit6,bit5,bit4,bit3,bit2,bit1,bit0 * 1 = output, 0 = input portd equ $1008 port d data register * - , - , ss* ,csk ;mosi,miso,txd ,rxd ddrd equ $1009 port d data direction register spcr equ $1028 spi control register * spie,spe ,dwom,mstr;spol,cpha,spr1,spr0 spsr equ $1029 spi status register * spif,wcol, - ,modf; - , - , - , - spdr equ $102a spi data register; read-buffer; write-shifter * * ram variables to hold the ltc1417s 14 conversion result * din1 equ $00 this memory location holds the ltc1417s bits 13 - 08 din2 equ $01 this memory location holds the ltc1417s bits 07 - 00 mux equ $02 this memory location holds the mux address data * ***************************************** * start getdata routine * ***************************************** * org $c000 program start location init1 ldaa #$03 0,0,0,0,0,0,1,1 * staf=0,stai=0,cwom=0,hnds=0, oin=0, pls=0, ega=1,invb=1 staa pioc ensures that the pioc registers status is the same * as after a reset, necessary of simple port d manipulation ldaa #$47 0,1,0,0,0,1,1,1 * bit7=input,bit6=output,- ,- ,- ,bit2=output,bit1=output, * bit0=output * bit7 used for busy input * bit6 used for convst signal output * bits 2 - 0 are used for the mux address staa ddrc direction of portds bit are now set ldaa #$2f -,-,1,0;1,1,1,1 * -, -, ss*-hi, sck-lo, mosi-hi, miso-hi, x, x staa portd keeps ss* a logic high when ddrd, bit5 is set ldaa #$38 -,-,1,1;1,0,0,0 staa ddrd ss* , sck, mosi are configured as outputs * miso, txd, rxd are configured as inputs * ddrds bit5 is a 1 so that port ds ss* pin is a general output ldaa #$50 staa spcr the spi is configured as master, cpha = 0, cpol = 0 * and the clock rate is e/2 * (this assumes an e-clock frequency of 4mhz. for higher
29 ltc1417 typical applicatio n s u * e-clock frequencies, change the above value of $50 to a * value that ensures the sck frequency is 2mhz or less.) getdatapshx pshy psha * ***************************************** * setup indecies * ***************************************** * ldx #$0 the x register is used as a pointer to the memory * locations that hold the conversion data ldy #$1000 * ***************************************** * initialize the ltc1417s convst input * * to a logic high before a conversion * * start * ***************************************** * bset portc,y %01000000 this sets portc, bit6 output to a logic * high, forcing convst to a logic high * ***************************************** * retrieve the mux address from memory * * and send it to the dg408 * ***************************************** * ldaa portc capture the contents of portc oraa mux add the mux address staa portc select the mux channel * ***************************************** * initiate a ltc1417 conversion * ***************************************** * bclr portc,y %01000000 this sets portc, bit6 output to a logic * low, initiating a conversion bset portc,y %01000000 this resets portc, bit6 output to a logic * high, returning convst to a logic high * ***************************************** * the next short loop ensures that the * * ltc1417s conversion is finished * * before starting the spi data transfer * ***************************************** * convendldaa portc retrieve the contents of port d anda #%10000000 look at bit7 * bit7 = hi; the ltc1417s conversion is complete * bit7 = lo; the ltc1417s conversion is not * complete bpl convend branch to the loops beginning while bit7 * remains high * ************************************************************************* * this routine sends data to the ltc1417 and sets its mux channel. the * * very first time this routine is entered produces invalid data. each * * time thereafter, the data will correspond to the previous active * * convst signal sent to the ltc1417. * ************************************************************************* *
30 ltc1417 typical applicatio n s u bclr portd,y %00100000 this sets the ss* output bit to a logic * low, selecting the ltc1417 trflp1 ldaa #$0 load accumulator a with a null byte for spi transfer staa spdr this writes the byte into the spi data register and * starts the transfer wait1 ldaa spsr this loop waits for the spi to complete a serial * transfer/exchange by reading the spi status register bpl wait1 the spif (spi transfer complete flag) bit is the spsrs * msb and is set to one at the end of an spi transfer. the * branch will occur while spif is a zero. ldaa spdr load accumulator a with the current byte of ltc1417 data * that was just received staa 0,x transfer the ltc1417s data to memory inx increment the pointer cpx #din2+1has the last byte been transferred/exchanged? bne trflp1 if the last byte has not been reached, then proceed to * the next byte for transfer/exchage bset portd,y %00100000 this sets the ss* output bit to a logic * high, de-selecting the ltc1417 ldd din1 load the contents of din1 and din2 into the double * accumulator d lsrd lsrd two logical shifts to right justify the 14-bit * conversion results std din1 return right justified data to memory pula restore the a register puly restore the y register pulx restore the x register rts convst busy sclk d out rd mux data ch5 ch3 data ch2 data ch1 data ch0 data ch0 ch1 ch2 ch3 1417 f24 figure 24. using the sample program in listing 2, the ltc1417, combined with the dg408 8-channel mux, has no latency between the selected input voltage and its conversion data as shown in the timing relationship above
31 ltc1417 u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) gn16 (ssop) 0398 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.025 (0.635) bsc 0.009 (0.229) ref information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
32 ltc1417 ? linear technology corporation 1999 1417fs sn1417 lt/tp 0100 4k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com related parts part number description comments adcs ltc1274/ltc1277 low power, 12-bit, 100ksps adcs with parallel output 10mw power dissipation, parallel/byte interface ltc1401 serial 3v, 12-bit, 200ksps adc in so-8 15mw, internal reference and low power shutdown mode ltc1404 serial 12-bit, 600ksps adc is so-8 5v or 5v, internal reference and shutdown ltc1412 12-bit, 3msps sampling adc with parallel output best dynamic performance, sinad = 72db at nyquist ltc1415 single 5v, 12-bit, 1.25msps adc with parallel output 55mw power dissipation, 72db sinad ltc1416 low power, 14-bit, 400ksps adc with parallel output 70mw power dissipation, 80.5db sinad ltc1418 low power, 14-bit, 200ksps adc with parallel and serial i/o true 14-bit linearity, 81.5db, sinad, 15mw dissipation ltc1419 low power, 14-bit, 800ksps adc with parallel output true 14-bit linearity, 81.5db sinad, 150mw dissipaton ltc1604 16-bit, 333ksps sampling adc with parallel output 2.5v input, 90db sinad, 100db thd ltc1605 single 5v, 16-bit, 100ksps adc with parallel output low power, 10v inputs, parallel/byte interface dacs ltc1595 serial 16-bit cmos mulitplying dac in so-8 1lsb max inl/dnl, 1nv ? sec glitch, dac8043 upgrade ltc1596 serial 16-bit cmos mulitplying dac 1lsb max inl/dnl, dac8143/ad7543 upgrade ltc1650 serial 16-bit 5v voltage output dac low noise and low glitch rail-to-rail v out ltc1655 serial 16-bit voltage output dac low power, so-8 with internal reference ltc1658 serial 14-bit voltage output dac low power, 8-lead msop rail-to-rail v out reference lt1019-2.5 precision bandgap reference 0.05% max, 5ppm/ c max lt1460-2.5 micropower 3-termainal bandgap reference 0.075% max, 10ppm/ c max lt1461-2.5 ultraprecise micropower low dropout reference 0.04%, 3ppm/ c

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